This invention relates to the field of integrated circuit (IC) design. Specifically, it relates to an embedded DRAM (eDRAM) system having a micro-cell architecture, a wide data bandwidth and a wide internal bus width implementing a high-speed, high-quality data protocol for data transfer operations.
Embedded DRAMs (eDRAMs) with wide data bandwidth and wide internal bus width have been proposed to be used as L2 (level-2) cache to replace pure SRAM cache. Since each DRAM memory cell is formed by a transistor and a capacitor, the size of DRAM cache is significantly smaller than that of SRAM cache. In order to meet performance requirements, an eDRAM is formed of a plurality of blocks or micro-cells. A bank is comprised of one or more blocks. A block is a small DRAM array unit formed by a plurality of wordlines (e.g., from 64 to 256) and a plurality of bitline pairs (e.g., from 64 to 256). The size of a block is much smaller (e.g., 16xc3x97 to 256xc3x97) than that of a bank of a conventional stand-alone DRAM. Typically one bank of each eDRAM bank is activated at a time. It is possible for blocks from different banks to be accessed simultaneously for simultaneous read and write operations. The read and write speed of an eDRAM can be fast due to very light loading of wordlines and bitlines.
An SRAM array is provided for effectively utilizing the large eDRAM cache size. The SRAM array, similar in size to an eDRAM block, is provided for serving as a cache interface in-between the eDRAM bank(s) and one or more processors and for facilitating a high-speed pipeline operation in the eDRAM
The wide internal bus (64-1024 Bits) is provided for transferring data between the eDRAM, SRAM and processor(s). Due to the high density of the wide internal bus, certain wiring regions for control and data lines are very small and difficult for providing a circuit layout.
To illustrate the high density of data transfer performed by the wide internal bus, the data bus includes read data lines (e.g., 144 read data lines) plus redundant data lines (e.g., 8 redundant data lines forming a total of 152 data lines in the read data bus). Data is transferred from an eDRAM micro-cell upon activation by a wordline. The data is first amplified by primary sense amplifiers and then by corresponding secondary sense amplifiers. The data is then passed through the read data bus to a central neck region for passing through a column redundancy switch circuit, and then on to an SRAM macro. As the data approaches the central neck region, it passes through congested areas in which data paths converge.
Accordingly, a need exists for providing a compact eDRAM system having a wide data bandwidth, high-capacity storage, and data paths conducive to high-speed and high-integrity read operations. Furthermore, a need exists for a read data protocol for directing stored data through data paths for achieving high-speed and high-integrity read operations in a high-capacity embedded DRAM macro having a wide data bandwidth. Furthermore, a need exists for a method and system for allowing sufficient time to accurately read data stored in a far location, and to prevent wasting time when reading data stored in a near location.
An aspect of the present invention is to provide a compact eDRAM system having a wide data bandwidth, high-capacity storage, and data paths conducive to high-speed and high-integrity read operations.
Another aspect of the present invention is to provide a read data protocol for directing stored data through read data paths for achieving high-speed and high-integrity read operations in a high-capacity embedded DRAM macro having a wide data bandwidth.
Another aspect of the present invention is to provide a method and system for allowing sufficient time to accurately read data stored in a far location, and to prevent wasting time when reading data stored in a near location.
Accordingly, a self-timed data communication system for a wide data width semiconductor memory system having a plurality of data banks configured for storing data is provided. The data communication system includes circuitry for transferring data having a plurality of data paths, wherein a corresponding data bank of the plurality of data banks is connected to a respective one data path of the plurality of data paths, and circuitry for controlling the respective one data path in accordance with receipt of a monitor signal indicating that a data transfer operation has been initiated for transfer of data to or from the respective one data path. The circuitry for controlling generates a control signal for controlling resetting of the respective one data path after data is transferred for preparation of a subsequent data transfer operation.
The circuitry for transferring data further includes a central data path including at least one junction circuit configured for exchanging data signals between the central data path and at least one data path of the plurality of data paths. A respective one junction circuit of the at least one junction circuit includes circuitry for controlling resetting the respective one junction circuit for preparation of a subsequent data transfer through the respective one junction circuit in accordance with receipt of an input junction monitor signal indicating that data has been transferred to the respective one junction circuit.